1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a self-aligned contact hole and a method for manufacturing the same.
2. Discussion of the Related Art
A general process of forming a self-aligned contact hole, which can be easily and precisely made, does not require fitting a mask using a location-fitting margin. Accordingly, high integration can be achieved without utilizing a highly skilled process or highly precise equipment to perform the process.
There are two conventional methods for forming a self-aligned contact hole. In one method, selective etch rates are used. In another method, which is a semi self-alignment method, a contact hole is formed and then an oxide sidewall is formed.
A conventional method for manufacturing a semiconductor device will be explained with reference to the accompanying drawings.
FIGS. 1a to 1c are cross-sectional views showing a method for manufacturing a semiconductor device according to one conventional method and FIGS. 2a to 2c are cross-sectional views showing a method for manufacturing a semiconductor device according to another conventional method. FIG. 3 is a cross-sectional view showing a structure of a semiconductor device manufactured according to a conventional method, which illustrates problems arising from manufacturing the semiconductor device according to a conventional method.
Referring initially to FIG. 1a, an active region and a field region are defined on a substrate 1 and then a field oxide layer is formed on the field region. Next, an oxide layer, a polysilicon layer, and a nitride layer are successively formed on the entire surface of the substrate 1. Subsequently, a photoresist layer is coated on the resultant surface and then selectively patterned. With the patterned photoresist layer serving as a mask, the nitride layer, the polysilicon layer, and the oxide layer are successively etched to form a first and second gate structure 3a and 3b, respectively. The first and second gate structures 3a and 3b comprise a gate oxide layer 2, a gate electrode 3, and a gate cap insulating layer 4. Thereafter, the remaining patterned photoresist layer is removed.
With the first and second gate structures 3a and 3b serving as a mask, lightly doped impurity ions are implanted into the exposed surface of the substrate 1 thereby forming lightly doped source and drain regions 5. Next, a nitride layer is deposited over the substrate 1 and anisotropically etched to form sidewall spacers 6 on the sides of the first and second gate structures 3a and 3b, respectively. With the first and second gate structures 3a and 3b and the sidewall spacers 6 serving as a mask, heavily doped impurity ions are implanted into the exposed surface of the substrate 1 thereby forming a heavily doped source/drain region 7.
Referring to FIG. 1b, there is formed an interlayer insulating layer 8 over the substrate 1. Then a photoresist layer is formed on the interlayer insulating layer 8 and exposed and developed to form the patterned photoresist layer 9.
Referring to FIG. 1c, with the patterned photoresist layer 9 serving as a mask, the interlayer insulating layer 8 is anisotropically etched using a high selective etch rate of the oxide and nitride layers until the surface of the substrate 1 is exposed, thus forming a contact hole. The high selective etch rate is described as the nitride or oxide layer being easily etched and the polysilicon layer not being easily etched or vice-versa. Next, on the entire surface of the substrate 1, there is formed a conductive material such as polysilicon, aluminum, or tungsten that are patterned to form a bit line 10. Another conventional method for manufacturing a semiconductor device will be explained with reference to FIGS. 2a-2c.
Referring initially to FIG. 2a, there are defined an active region and a field region in the substrate 11. A field oxide layer is formed on the field region. Then, a first oxide layer, a polysilicon layer, and a second oxide layer are successively formed on the entire surface of the substrate 11. Subsequently, a photoresist layer is coated on the resultant surface and then exposed and developed to form a patterned photoresist layer. With the patterned photoresist layer serving as a mask, the first oxide layer, the polysilicon layer, and the second oxide layer are successively etched to form a first and second gate structure 13a and 13b, respectively. The first and second gate structures 3a and 3b comprise a gate oxide layer 12, a gate electrode 13, and a gate cap insulating layer 14 on a predetermined portion of the substrate 11. Thereafter, the remaining patterned photoresist layer is removed.
With the first and second gate structures 13a and 13b serving as a mask, lightly doped impurity ions are implanted into the exposed surface of the substrate 11 thereby forming lightly doped source and drain regions 15. Next, an oxide layer is formed on the resultant surface and then anisotropically etched to form sidewall spacers 16 on sides of the first and second gate structures 13a and 13b. With the sidewall spacers 16 and first and second gate structures 13a and 13b serving as a mask, heavily doped impurity ions are implanted into the substrate 11 thereby forming a heavily doped source/drain region 17.
Referring to FIG. 2b, on the resultant surface, there is deposited an interlayer insulating layer 18 using a chemical vapor deposition (CVD) method. Next, a photoresist layer is coated on the resultant surface and then exposed and developed to form a patterned photoresist layer 19.
Referring to FIG. 2c, with the patterned photoresist layer 19 serving as a mask, the interlayer insulating layer 18 is anisotropically etched in between the first and second gate structures 13a and 13b to expose the surface of the source/drain region 17 thereby forming a contact hole. Then, an oxide layer is formed on the resultant surface and then anisotropically etched to form oxide sidewall spacers 20 on sides of the interlayer insulating layer 8. Subsequently, a conductive material such as polysilicon, aluminum, or tungsten is formed on the entire surface and then patterned to form a bit line 21. In this case, the oxide sidewall spacers 20 serve to insulate the gate electrode 13 from the bit line 21.
Problems arising from semiconductor devices manufactured according to the conventional methods will be explained with reference to FIG. 3.
As shown in FIG. 3, when an alignment tolerance is beyond the limit of a photolithography process, formation of a contact hole is misaligned on a gate electrode 13. Consequently, a short between the gate electrode 13 and the bit line 21 is generated even after the oxide sidewall spacers 20 are formed.
Conventional methods for manufacturing a semiconductor device have the following problems.
First, it is difficult to carry out an etch process over materials such as a nitride and an oxide having a high selective etch rate. If a selective etch rate is high, a polymer may be generated that blocks a contact hole and stops the etch process. Moreover, it is difficult to simplify the overall process.
Second, for a high density device, alignment tolerance easily goes beyond the limit of a photolithography process that causes misalignment when forming a contact hole. Because of misalignment, a short between a gate electrode and a bit line is generated that destroys the operability of a unit device.